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職責(zé)描述： 與設(shè)計(jì)架構(gòu)師緊密合作，參與架構(gòu)級(jí)別的討論。 IP級(jí)設(shè)計(jì)規(guī)范和RTL編碼 與綜合和物理設(shè)計(jì)團(tuán)隊(duì)合作制定ASIC實(shí)施計(jì)劃。 與驗(yàn)證工程師合作完成功能/性能測(cè)試計(jì)劃。 任職要求： 2年或3年以上ASIC/SoC設(shè)計(jì)經(jīng)驗(yàn) 較強(qiáng)的verilog開(kāi)發(fā)實(shí)踐經(jīng)驗(yàn) 熟悉Perl、Makefile、 熟悉DSP, ARM, AXI優(yōu)先考慮 熟悉內(nèi)存控制器，有PCIE優(yōu)先考慮。 較強(qiáng)的問(wèn)題解決能力，團(tuán)隊(duì)合作和溝通能力 Participate in architecture level discussion by closely working with design architects. IP level design spec and RTL coding Coworking with synthesis and physical design team on the ASIC implementation plan. Coworking with verification engineers on the function/performance test plan. 任職要求：MS with 2 years or BS with 3 years’ experience in ASIC/SoC design Strong hands-on verilog development experience Familiar with scripting languages like Perl, Makefile, … Familiar with DSP, ARM, AXI is a plus Knowledge on memory controller, PCIE is a big plus. Strong problem solving, teamwork and communication skills