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Responsibilities: DFT Engineer is responsible for the DFT design and verification of ASIC chips, including test architecture definition, scan chain insertion, scan compression, Memory BIST insertion, ATPG, test structure verification and etc. Capable to define and deliver competitive DFT solution with optimized test cost, high test coverage, low test power and short TAT. Design, implement and verify other DFX (debug, characterization, yield etc) feature Requirements: 1.ME/EE or background in related areas. 2.At least 2 years of industry working experience of chip DFT design and verification. 3.Solid experience using Mentor Tessent on Memory BIST insertion and verification is a STRONG plus. 4.Proficient in Verilog/VHDL, and well conversant with programming and script languages. 5.Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus. 6.Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.